Parallel testing is a traditional ATE technique to increase throughput without a corresponding increase in cost, by performing tests on multiple devices-under-test (DUTs) at the same time. Low-cost ATE has often been promoted as a solution to reduce the cost of test. Parallel testing is another approach, which has been shown to reduce test cost more effectively than low-cost ATE by J. Rivoir in “Lowering Cost of Test: Parallel Test or Low-Cost ATE?” Proc. 12th, Asian Test Symposium, November 2003, pp. 361-368. This is because parallel testing reduces all factors contributing to the cost of testing, and not just the capital cost of ATE. An analysis of test benchmarking data is given in “Comparison of Final Test Handling Strategies for Massively Parallel Test of Logic Devices,” by P. Cochran, etc. in Future Fab International, Vol. 12, Feb. 2002. The analysis indicates that maximizing parallelism impacts the cost of test to a great degree. According to Cochran, up to a 50% reduction in test cost was observed by testing four devices in parallel instead of each one serially.
There has long been significant interest in achieving efficient multi-DUT testing, through either scan-based techniques or traditional ATE parallel test techniques. An example of the scan-based techniques is described in “Scan-based Testing: The Only Practical Solution for Testing ASIC/Consumer Products,” by P. Nigh in Proc. 2002 IEEE International Test Conference, October 2002, pp. 1198. Examples of traditional ATE parallel test techniques are described in “Pattern Based Test: Key to Parallel Test Efficiency in Multi-Site Analog and Mixed-Signal Device Testing,” by J. Weimer, and also described in “Parallel Test Reduces Cost of Test More Effectively than Just a Cheaper Tester,” by J. Rivoir, both papers to be presented at the 7th European Manufacturing Test Conference, April 2005. The above publications are incorporated herein in their entirety by reference. Hence, many ATE manufacturers currently support parallel multi-DUT testing in one form or another.
For example, parallel testing is supported by Advantest Corporation's T2000 system through its multi-Site Controller environment. As shown in FIG. 1, each Site Controller (SiteC) 104 is responsible for controlling a single DUT 108 through a vendor hardware module 106, while the System Controller (SysC) 102 runs multiple SiteCs 104 concurrently. Such a multi-SiteC environment is more suited for System-on-Chip (SOC) device testing applications, because of the intensive and time-consuming data analysis requirements, such as fast Fourier transform (FFT) analyses, which are typically found in SOC devices.
However, it is a rather restricted market segment that can afford the extra cost of manufacturing high-value devices with larger pin counts. Many integrated circuit (IC) devices are inexpensive, and have smaller pin counts. A smaller device requires less hardware resources, in general, which implies that a larger number of smaller DUTs can be tested at the same time than bigger DUTs. If testing each smaller DUT were to require an entire SiteC, the cost of the ATE system and the cost of testing would increase accordingly. This cost versus throughput trade-off makes a single SiteC-based parallel test system quite desirable. Therefore, there is a need for performing parallel testing with a single SiteC, and there is a need for scheduling tests efficiently in testing multiple DUTs coupled to a single SiteC in a parallel test system.